Got introduced to a flashy new CAD item today. Synopsys PrimePower, fresh out of the box (we're the first in the lab to use it, at least). We need it to verify (and improve) our BTP results, the tool helps in carrying out accurate power simulations, pleasantly opposed to synthesis estimates. We really wish this works (and supports our claims).
Grabbing the license for our linux accounts took close to three discouraging hours. When we finally got it, we were able to launch the exceedingly user-unfriendly GUI. I don't blame it though, it usually takes one PhD (and some more) to be able to operate such a tool at attempt #1. Slight tinkering did nothing, major tinkering nearly shut the system off. As the last resort we decided to read the manual.
Poorly written yet again, it took us hours to find what those guys really wanted by a db file, and where we could get it. The manual failed, and our friend Anoop had to help us to it.
This means we'd learned the following commands:
set searchpath
set link_path
We then moved on to ACTUALLY loading a verilog file (and testbench) using read_verilog, but the darned thing refused to work. In sequence, it posed the following problems:
1. The tool only compiles structural Verilog, *unless* you use the -hdl_compiler option. We dug the manual for 20 minutes to discover it.
2. It hates to accept that a testbench can ever be linked with the DUT. It assigns a blackbox to the latter.
3. PrimePower denies existence of any files we `include in code.
4. PrimePower assigns blackboxes to about two million lines of output before freezing, and on our intervention, dying.
Fortunately, there are absolutely NO tutorials/help online. CADastrophic.
I wait in agony for the success of my third command.
Grabbing the license for our linux accounts took close to three discouraging hours. When we finally got it, we were able to launch the exceedingly user-unfriendly GUI. I don't blame it though, it usually takes one PhD (and some more) to be able to operate such a tool at attempt #1. Slight tinkering did nothing, major tinkering nearly shut the system off. As the last resort we decided to read the manual.
Poorly written yet again, it took us hours to find what those guys really wanted by a db file, and where we could get it. The manual failed, and our friend Anoop had to help us to it.
This means we'd learned the following commands:
set searchpath
set link_path
We then moved on to ACTUALLY loading a verilog file (and testbench) using read_verilog, but the darned thing refused to work. In sequence, it posed the following problems:
1. The tool only compiles structural Verilog, *unless* you use the -hdl_compiler option. We dug the manual for 20 minutes to discover it.
2. It hates to accept that a testbench can ever be linked with the DUT. It assigns a blackbox to the latter.
3. PrimePower denies existence of any files we `include in code.
4. PrimePower assigns blackboxes to about two million lines of output before freezing, and on our intervention, dying.
Fortunately, there are absolutely NO tutorials/help online. CADastrophic.
I wait in agony for the success of my third command.
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